The present invention relates generally to the field of semiconductor metrology and inspection. More specifically, it relates to techniques for minimizing tool-induced shift during overlay metrology.
Lithography tools used in the manufacture of integrated circuits have been around for some time. Such tools have proven extremely effective in the precise manufacturing and formation of very small details in the product. In most lithography tools, a circuit image is written on a substrate by transferring a pattern via a light beam. For example, the lithography tool may include a light source that projects a circuit image through a reticle and onto a silicon wafer coated with photoresist. The exposed photoresist typically forms a pattern that masks the layers of the wafer during subsequent processing steps, as for example deposition and/or etching. As is generally well known, materials are deposited onto the layers of the wafer during deposition and materials are selectively removed from the layers of the wafer during etching.
The measurement of overlay between successive patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it. Presently, overlay measurements are performed via targets that are printed together with layers of the wafer. The most commonly used overlay target pattern is the “Box-in-Box” target, which includes a pair of concentric squares (or boxes) that are formed on successive layers of the wafer. The overlay error is generally determined by comparing the position of one square relative to the other square. This may be accomplished with an overlay metrology tool that measures the relative displacement between the two squares.
Most overlay measurements are performed immediately after the photoresist is developed, i.e., the photoresist is developed away in the area where it was exposed to the light thus leaving the overlay pattern in the photoresist. Overlay measurements can also be performed after process steps such as etch, when no photoresist is present.
To facilitate discussion, FIG. 1 is a top view of a typical “Box-in-Box” target 2. As shown, the target 2 includes an inner box 4 disposed within an open-centered outer box 6. The inner box 4 is printed on the top layer of the wafer while the outer box 6 is printed on the layer directly below the top layer of the wafer. As is generally well known, the overlay error between the two boxes, along the x-axis for example, is determined by calculating the locations of the edges of lines c1 and c2 of the outer box 6, and the edge locations of the lines c3 and c4 of the inner box 4, and then comparing the average separation between lines c1 and c3 with the average separation between lines c2 and c4. Half of the difference between the average separations c1 & c3 and c2 & c4 is the overlay error (along the x-axis) at that point. Thus, if the average spacing between lines c1 and c3 is the same as the average spacing between lines c2 and c4, the corresponding overlay error tends to be zero. Although not described, the overlay error between the two boxes along the y-axis may also be determined using the above technique.
A significant factor which affects the accuracy of the measured overlay is referred to as “tool-induced shift” or TIS which depends on the optical aberrations present in the optical column of the metrology tool. TIS generally causes the measured overlay to shift and results in the measured overlay differing from the “real” overlay value. TIS is also target dependent and some targets will have a greater or lesser overlay shift on the same metrology tool.
One goal in overlay metrology is to reduce the amount of TIS present in the measured overlay value. One technique includes searching for a focus position on the metrology tool which results in the best (or lowest) TIS. Although this technique works well to reduce TIS, it has several disadvantages. Changing the measurement focus position also affects the TIS corrected overlay value. Since each metrology tool requires a different optimal focus position, the effect on the overlay cannot be readily ascertained and subtracted from the overlay result across various metrology tools. Additionally, a small adjustment of the focus position can cause a significant reduction in the image contrast and adversely affect the measurement precision.
In view of the foregoing, there is a need for improved mechanisms for reducing TIS during overlay metrology. Additionally, reducing the TIS during overlay metrology without changing the measurement focus position is also desirable.